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F72830
Four-Phase Linear Controller with I2C Interface
Release Date: July, 2007 Version: 0.14P
Fintek
Feature Integration Technology Inc.
F72830 F72830 Datasheet Revision History
Version 0.10P 0.11P 0.12P
Date Sep, 2006 Sep, 2006 Dec, 2006
Page Preliminary version 18 4 5 Register-Chip ID Pin configuration Pin 9, GND VSS
Revision History
EN pin description 7 8 21 0.13P 0.14P Feb, 2007 Jul, 2007 7 20 Electrical characteristic, VCC Input high voltage: 2V Application circuit 1.5V VDDA
VREF Range: 0.79~0.83V, typical: 0.8V
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Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Fintek for any damages resulting from such improper use or sales.
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F72830 Table of Contents
1 2 3 4 5
GENERAL DESCRIPTION ........................................................................................................................................................ 3 FEATURE ..................................................................................................................................................................................... 3 PIN CONFIGURATION .............................................................................................................................................................. 4 PIN DESCRIPTION..................................................................................................................................................................... 4 ELECTRICAL CHARACTERISTIC......................................................................................................................................... 6 5.1 5.2 5.3 ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................... 6 DC AND AC ELECTRICAL CHARACTERISTICS (VDDA = 5V, TA = 25) ................................................................................... 7 SPECIFICATION OF RELIABILITY................................................................................................................................................ 8
6 7 8
BLOCK DIAGRAM ..................................................................................................................................................................... 9 SIMPLIFIED EXTERNAL APPLICATION DIAGRAM....................................................................................................... 10 FUNCTIONAL DESCRIPTION ............................................................................................................................................... 10 8.1 8.2 8.3 8.4 LINEAR CONTROLLER DESCRIPTION....................................................................................................................................... 10 SOFT-START ............................................................................................................................................................................ 11 UNDER VOLTAGE PROTECTION................................................................................................................................................ 13 ACCESS INTERFACE ................................................................................................................................................................ 13
9
REGISTER DESCRIPTION ..................................................................................................................................................... 15 9.1 LR_1, LR_2 Fine Tune Voltage Register Index 1.................................................................................................................. 15 9.2 LR_3, LR_4 Fine Tune Voltage Register Index 2.................................................................................................................. 16 9.3 Under Voltage, Over Current Enable Protection Register Index 03h .................................................................................... 17 9.4 Reserved Function, Read back SSOK Status, If LR finished Soft Start, it Will Read back 1 Register Index 04h ................ 17 9.5 CHIP ID 1 INDEX 5AH............................................................................................................................................................ 18 9.6 CHIP ID 2 Index 5Bh ............................................................................................................................................................ 18
10 ORDERING INFORMATION .................................................................................................................................................. 19 11 PACKAGE DIMENSIONS (16-SOP) ....................................................................................................................................... 20 12 APPLICATION CIRCUIT ........................................................................................................................................................ 21
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F72830
1 General Description
The F72830 is a quadro MOSFET drivers specifically designed to drive quadro power N-Channel MOSFETs as a four-phase linear regulators. The device contains under voltage protection for every linear controller, an external ceramic capacitor to adjust slew rate of soft-start, and integrated I2C interface. The built-in I2C interface provides the function to fine tune the output of every linear controller from 0.74V to 1.04V, 0.02V per step, and the default output is set to 0.8V. The F72830 also offers 3 independent enable pins to control the corresponding linear controller. Linear controller 1 is active as power on, and other remained linear controller 2~4 are controlled by enable pin, EN2~4. Except being a regular linear controller, the F72830 can be paired with the chip, which contains AMD K8 power on/off timing sequence to be used a platform power supplier, for example, F71863, or any specific purpose. The chip is a 16pin SOP package and powered by 5/12V.
2 Feature
4 Channels of Linear Controller Supported Controlled by 3 Enable Pins: Linear Controller 1 Will Be Active as Power on Linear Controller 2~4 Can Be Active in any Sequence or at the Same Time(in 3CLK Debounce) Under Voltage Protection of All Linear Controllers External Capacitor for Adjusting Soft-start Slew Rate Integrated I2C Interface to Fine Tune Output of Linear Controller from 0.74V to 1.04V, 0.02V per Step, Typical Output Is 0.8V Independent Enable Pin Controls Single Linear Controller On/Off Individually Powered by VVDDA: 5~12V 16-SOP Green Package
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F72830
3 Pin Configuration
Figure1. F72830 pin configuration
4 Pin Description
I/OD12st INst - TTL level bi-directional pin with schmitt trigger., Open-drain outpu with 12 mA sink capability. - TTL level input pin with schmitt trigger.
AIN - Input pin(Analog). AOUT P - Output pin(Analog). - Power.
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Power Pins PIN NO 9 16 PIN NAME VSS VDDA TYPE P Power pins
Feature Integration Technology Inc.
F72830
DESCRIPTION
Control signal PIN NO 10 11 12 PIN NAME EN2 EN3 EN4 TYPE INts INts INts PWR VDD VDD VDD DESCRIPTION Linear driver2 control signal input, input voltage > 1.5V, L Linear driver3 control signal input, input voltage > 1.5V, L Linear driver4 control signal input, input voltage > 1.5V, L H H H
Switching Signal & Linear/PWM Controller PIN NO PIN NAME TYPE PWR DESCRIPTION Sense the voltage of linear regulator. LR1_SEN and LR1_DRV 1 LR1_SEN AIN VDD act as a linear regulator. The linear controller 1 will act while powering on the chip and finishing soft-start. Connect this pin to the gate of a suitable N-channel MOSFET. 2 LR1_DRV AOUT VDDA LR1_SEN and LR1_DRV act as a linear regulator. The linear controller 1 will act while powering on the chip and finishing soft-start. Connect this pin to the gate of a suitable N-channel MOSFET. LR2_SEN and LR2_DRV act as a linear regulator. The linear 3 LR2_DRV AOUT VDDA controller 2 will act when the input of EN2 acts high. The linear controller 2 will be off when the input of EN2 acts low. Sense the voltage of linear regulator. LR2_SEN and LR2_DRV act as a linear regulator. The linear controller 2 will act when the 4 LR2_SEN AIN VDD input of EN2 acts high. The linear controller 2 will be off when the input of EN2 acts low. Sense the voltage of linear regulator. LR3_SEN and LR3_DRV act as a linear regulator. The linear controller 3 will act when the 5 LR3_SEN AIN VDDA input of EN3 acts high. The linear controller 3 will be off when the input of EN3 acts low.
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F72830
Connect this pin to the gate of a suitable N-channel MOSFET. LR3_SEN and LR3_DRV act as a linear regulator. The linear 6 LR3_DRV AOUT VDDA controller 3 will act when the input of EN3 acts high. The linear controller 3 will be off when the input of EN3 acts low. Sense the voltage of linear regulator. LR4_SEN and LR4_DRV 7 LR4_DRV AOUT VDDA act as a linear regulator. The linear controller 4 will act when the input of EN4 acts high. The linear controller 4 will be off when the input of EN4 acts low. Connect this pin to the gate of a suitable N-channel MOSFET. LR4_SEN and LR4_DRV act as a linear regulator. The linear 8 LR4_SEN AIN VDD controller 4 will act when the input of EN4 acts high. The linear controller 4 will be off when the input of EN4 acts low.
Others PIN NO 14 13 PIN NAME SCLK SDATA TYPE INts I/OD12ts PWR VDD VDD DESCRIPTION I2C serial bus clock I2C serial bus data Soft-Start. Connect this pin to a small ceramic capacitor to 15 SS AIN VDD determine the soft-start rate. The value of capacitor is bigger, the slew rate is slower. * The VDD is the internal voltage which is a step-down voltage generated from input voltage, VDDA.
5 Electrical Characteristic
5.1 Absolute Maximum Ratings
PARAMETER IC supply voltage ESD classification
SYMBOL VDDA HBM
RATINGS 17 2
UNIT V kV
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Maximum junction temperature (plastic package) Maximum storage temperature Maximum lead temperature (soldering 10s)
Feature Integration Technology Inc.
F72830
Tj TSTO 150 -65 ~ 150 260 C C C
Note: If ICs are stressed beyond the limits listed in the "absolute maximum ratings", they may be permanently destroyed. These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
Package thermal information PARAMETER Thermal resistance junction-ambient SYMBOL Rth_ja SOIC 57 UNIT C/W
Recommended Operating Conditions
Supply Voltage, VDDA ----------------------------------------------------------------------------------Ambient Temperature Range----------------------------------------------------------------------Junction Temperature Range-----------------------------------------------------------------------
5V~12V 10% 0C to 70C 0C to 125C
5.2 DC and AC electrical characteristics (VDDA = 5V, TA = 25)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDDA SUPPLY CURRENT/Regulated Voltage Nominal supply current POWER-ON RESET Rising VDDA threshold Falling VDDA threshold OSCILLATOR AND Protection Free running frequency Soft-start interval REFERENCE VOLTAGE Reference voltage LINEAR REGULATOR VREF VDDA=12V, T= 25 0.79 0.8 0.83 V FOSC TSS 200 250 12 300 kHz uA 3.0 2.7 3.3 3.0 3.6 3.3 V V IVDDA 5 10 mA
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PARAMETER DC gain Gain-bandwidth product Under voltage level
: Design Guarantee
Feature Integration Technology Inc.
F72830
SYMBOL A0 GBWP VUV CL = 1000pF Percent of nominal TEST CONDITIONS MIN. 0.3 TYP. 70 1.86 0.4 MAX. 0.5 UNIT dB MHz V
I/O PAD DC Characteristics (Ta = 0 C to 70 C, VDDA = 5~12V 10%, VSS = 0V)
PARAMETER Input Low Voltage Input High Voltage Output Low Current Input High Leakage Input Low Leakage Input Low Voltage Input High Voltage Output Low Current Input High Leakage Input Low Leakage Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage Output Low Current
SYM. VIL VIH IOL ILIH ILIL VIL VIH IOL ILIH ILIL VIL VIH ILIH ILIL IOL
MIN.
TYP.
MAX. 0.8
UNIT V V mA
CONDITIONS VDDA =5~12V VDDA = 5~12V VOL = 0.4V VIN = 3.3V VIN = 0V VDDA =5~12V VDDA = 5~12V VOL = 0.4 V VIN = 3.3V VIN = 0V
I/OD12st-TTL level bi-directional pin with schmitt trigger, Open-drain output with12 mA sink capability. 1.5 +12 +1 -1 0.8 1.5 -12 +1 -1 0.8 1.5 +1 -1 -12
A A V V mA A A V V A A mA
I/O12st- TTL level bi-directional pin with schmitt trigger and with 12mA source-sink capability.
INst - TTL level input pin with schmitt trigger
VIN = 3.3V VIN = 0 V VOL = 0.4V
OD12-Open-drain output with12 mA sink capability.
5.3 Specification of Reliability
Test Item ESD Latch-UP
Description VHBM > 2KV, VMM > 200V Itr => 50~ 100mA
Y/N
Test Item TH(B) PCT
Description 1000Hrs, 85% RH, 85 168 Hrs, 100% RH , 121
Y/N
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F72830
6 Block Diagram
VDDA
VDDA BandGap Bias & SS Power On Reset REG3V VDD 0.8V
LR1_DRV LR1_SEN
SS
VDDA 0.8V
LR1_UV
0.4V VDDA 0.8V
LR3_DRV LR3_SEN
0.4V VDDA 0.8V
LR2_DRV LR3_UV I2C Interface, ACPI Control Circuit, VFB fine tune voltage LR2_UV LR2_SEN
0.4V
LR4_DRV LR4_SEN
0.4V
LR4_UV
SCL SDA
Figure2. F72830 block diagram
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F72830
7 Simplified External Application Diagram
PWR
SDA SCL
I2C & ACPI Control
LR1 LR Controllers LR Application circuit LR2 LR3 LR4
Figure3. F72830 external application diagram
8 Functional Description
8.1 Linear Controller Description
The F72830 contains 4 sets of linear controllers. When the chip is powered on, soft-start will be active. Then, the first linear controller will generate the output voltage. The other 3 sets of linear controllers, LR_2, LR_3, and LR_4 are controlled by the corresponding enable pin, EN2, EN3, and EN4. There is no priorities in linear controllers 2~4. The output voltage sequence of linear controllers 2~4 issued depends on enable signal of EN2~4 sequence only. If any enable pin acts high before or at the same time as VDDA PWROK, the corresponding linear controller will generate output as linear controller 1 simultaneously. When the enable pin receives enable signal, soft-start and enable status checking will be active. To receive first coming high signal from any enable pin then soft-start will start. Before the duration of soft-start reaching 0.1V, any successive acting high enable signal is considered in the same soft-start sequence. All of the linear regulators corresponding to high acting enable pins will generate output following soft-start procedure. If the successive enable signal is received out of the bound of the duration, the enable sequence will be arranged after this period of soft-start finishes. The detail can be referred in Figure4.
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F72830
1.6V
0.1V PAD_SS SS_LOW
Allowed Soft start Active region Soft Start can't be active regionAllowed Soft start Active region EN2 EN3 EN4
Figure4. F72830 enable and Soft Start Timing Chart
8.2 Soft-start
Pin15 of the F72830 acts as soft-start function. As shown in schematic, a ceramic capacitor is attached between this pin and ground. When power is first applied to the chip, a constant current is applied from the pin into an external capacitor, linearly ramping up the voltage. This ramp in turn controls the internal reference of F72830 providing a soft-start for linear regulator. As for switches, they must be either on or off in the system therefore soft-start has no effect on them. It is important to know soft-start is not an enable signal; pulling it low will not be sure to turn off all outputs. But if there are appropriate signals asserted, the switches will be turn on at once. The actual state of F72830 on power up will be determined by the controlled input signal. And the soft-start is effective only during power on. The detail timing chart could be shown as Figure 5.
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F72830
3.3v VDDA RESET_N LR1_SS LR1_DRV EN_2 LR2_SS 3clk debounce LR2_DRV EN_3 LR3_SS 3clk debounce LR3_DRV EN_4 LR4_SS 3clk debounce LR4_DRV 3clk debounce 3clk debounce 50u
3.0v
SD LR1
SD LR2
SD LR3
3clk debounce SD LR4
Note that: LR1, LR2, LR3, and LR4 can be active at the same time or not. (if you want to let the LR2, LR3, and LR4 soft start at the same time, EN_2, EN_3, and EN_4 should be high before SS under 0.1V. It is recommended to set high at the same time, if you want to let the linear regulators soft start at the same time. If you set high after SS is higher than 0.1v, it will wait the soft start finished, and begin the next soft start). If LR2~LR4 are desired to act as LR1 while power on, EN2~ EN4 must be pulled high before VDDA reaches PWROK. Figure5. Soft-start timing and indication
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8.3 Under voltage protection
Feature Integration Technology Inc.
F72830
If the LR_SEN voltage drops below 0.4V, a fault signal is generated. When under voltage condition occurs, the related Linear Regulator will shut down.
8.4 Access interface
The F72830 can be connected to a compatible 2-wire serial system Management Bus (SMBus) as a slave device under the control of the master device, using two device terminals SCL and SDA. The controller can provide a clock signal to the device SCL pin and read/write data from/to the device through the device SDA pin. The address default is 0x5E(0101_1110) and the operation of device to the bus is described with details in the following sections.
(a) SMBus write to internal address register followed by the data byte
0 SCLK SDA
Start By Master
7
8
0
7
8
0
1
0
1
1
1
1
R/W
Ack by 830
D7
D6
D5
D4
D3
D2
D1
D0
Ack by 569
Frame 1 Serial Bus Address Byte 0
Frame 2 Internal Index Register Byte
7 SCL (Continued) SDA (Continued) D7 D6 D5 D4 D3 D2 D1 D0
8
Frame 3 Data Byte
Stop by Master
Figure 6. Serial Bus Write to Internal Address Register followed by the
(b) Serial bus write to internal address register only
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F72830
0 SCL SDA
Start By Master
7
8
0
7
8
0
1
0
1
1
1
1
R/W
Ack by 830
D7
D6
D5
D4
D3
D2
D1
D0
Ack by 569 Stop by Master
Frame 1 Serial Bus Address Byte 0
Frame 2 Internal Index Register Byte
Figure 7. Serial Bus Write to Internal Address Register Only
(c) Serial bus read from a register with the internal address register prefer to desired location
0 SCL SDA
Start By Master
7
8
0
7
8
0
1
0
1
1
1
1
R/W
Ack by 830
D7
D6
D5
D4
D3
D2
D1
D0
Ack Stop by by Master Master
Frame 1 Serial Bus Address Byte 1
Frame 2 Internal Index Register Byte
Figure 8. Serial Bus Read from Internal Address Register
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9 Register Description
9.1 LR_1, LR_2 Fine Tune Voltage Register Index 1
Bit
Name
R/W
Default
Description Fine tune LR_1 reference voltage, LR1 Voltage table is set by Register 01h bit 7:4. 0000 : 0.74V 0001 : 0.76V 1000 : 0.90V 1001 : 0.92V 1010 : 0.94V 1011 : 0.96V 1100 : 0.98V 1101 : 1.00V 1110 : 1.02V 1111 : 1.04V
7:4
LR_1
R/W
3
0010 : 0.78V 0011 : 0.80V 0100 : 0.82V 0101 : 0.84V 0110 : 0.86V 0111 : 0.88V
Fine tune LR_2 reference voltage, LR2 Voltage table is set by Register 01h bit 3:0. 0000 : 0.74V 0001 : 0.76V 3:0 LR_2 R/W 3 0010 : 0.78V 0011 : 0.80V 0100 : 0.82V 0101 : 0.84V 0110 : 0.86V 0111 : 0.88V 1000 : 0.90V 1001 : 0.92V 1010 : 0.94V 1011 : 0.96V 1100 : 0.98V 1101 : 1.00V 1110 : 1.02V 1111 : 1.04V
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9.2 LR_3, LR_4 Fine Tune Voltage Register Index 2
Bit
Name
R/W
Default
Description Fine tune LR_3 reference voltage, LR3 Voltage table is set by Register 02h bit 7:4. 0000 : 0.74V 0001 : 0.76V 1000 : 0.90V 1001 : 0.92V 1010 : 0.94V 1011 : 0.96V 1100 : 0.98V 1101 : 1.00V 1110 : 1.02V 1111 : 1.04V
7:4
LR_3
R/W
3
0010 : 0.78V 0011 : 0.80V 0100 : 0.82V 0101 : 0.84V 0110 : 0.86V 0111 : 0.88V
Fine tune LR_4 reference voltage, LR4 Voltage table is set by Register 02h bit 3:0. 0000 : 0.74V 0001 : 0.76V 3:0 LR_4 R/W 3 0010 : 0.78V 0011 : 0.80V 0100 : 0.82V 0101 : 0.84V 0110 : 0.86V 0111 : 0.88V 1000 : 0.90V 1001 : 0.92V 1010 : 0.94V 1011 : 0.96V 1100 : 0.98V 1101 : 1.00V 1110 : 1.02V 1111 : 1.04V
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9.3 Under Voltage, Over Current Enable Protection Register Index 03h
Bit 7 6 5 4 3 2 1 0
Name Reserved Reserved Reserved SAME_UV LR1_UVEN LR2_UVEN LR3_UVEN LR4_UVEN
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default 1 0 0 0 1 1 1 1 Reserved Register Reserved Register Reserved Register
Description
If set to 1, one of 4 LR occurs UV, it will shut down all LR LR1 Under voltage enable LR2 Under voltage enable LR3 Under voltage enable LR4 Under voltage enable
9.4 Reserved Function, Read back SSOK Status, If LR finished Soft Start, it Will Read back 1 Register Index
04h
Bit 7
Name SOFT_SD_LR1
R/W R/W
Default 0 0
Description If set to 1, LR1 will SD, and if set to 0, and the Power is higher than internal PWROK, it will re-soft start. If set to 1, LR2 will SD, and if set to 0, it will detect EN2 high to do soft start
6
SOFT_SD_LR2
R/W
5
SOFT_SD_LR3
R/W
0
If set to 1, LR3 will SD, and if set to 0, it will detect EN3 high to do soft start
0 4 3 2 1 0 SOFT_SD_LR4 LATCH_S1_SSOK LATCH_S2_SSOK LATCH_S3_SSOK LATCH_S4_SSOK R/W R R R R 0 0 0 0
If set to 1, LR4 will SD, and if set to 0, it will detect EN4 high to do soft start If LR1 finished soft start, it will read back 1 If LR2 finished soft start, it will read back 1 If LR3 finished soft start, it will read back 1 If LR4 finished soft start, it will read back 1
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9.5 CHIP ID 1 Index 5Ah
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F72830
Bit 7 6 5 4 3 2 1 0
Name
R/W
Default 0 0 0 0
Description
CHIP ID 1
R
0 1 1 0
CHIP_ID1 = 8'h06;
9.6 CHIP ID 2 Index 5Bh
Bit 7 6 5 4 3 2 1 0
Name
R/W
Default 0 0 0
Description
CHIP ID 2
R
0 0 0 1 1
CHIP_ID1 = 8'h03;
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10 Ordering Information
Part Number F72830SG Package Type 16-SOP (Green Package) Production Flow Commercial, 0C to +70C
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F72830
11 Package Dimensions (16-SOP)
Figure9. 16 Pin SOP Package Diagram
Feature Integration Technology Inc.
Headquarters 3F-7, No 36, Tai Yuan St., Chupei City, Hsinchu, Taiwan 302, R.O.C. TEL : 886-3-5600168 FAX : 886-3-5600166 www: http://www.fintek.com.tw
Taipei Office Bldg. K4, 7F, No.700, Chung Cheng Rd., Chungho City, Taipei, Taiwan 235, R.O.C. TEL : 866-2-8227-8027 FAX : 866-2-8227-8037
Please note that all datasheet and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this datasheet belong to their respective owner
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Fintek 12 Application Circuit
U1 LR1_SEN LR1_DRV LR2_DRV LR2_SEN LR3_SEN LR3_DRV LR4_DEV LR4_SEN 1 2 3 4 5 6 7 8
Feature Integration Technology Inc.
F72830
+12V 16 15 14 13 12 11 10 09 C2 0.1u
LR1_SEN VDDA LR1_DRV SS LR2_DRV SCL LR2_SEN SDA EN4 LR3_SEN LR3_DRV EN3 LR4_DRV EN2 LR4_SEN GND F72830
C1 0.1u SCL SDA EN4 EN3 EN2
VCC3_3V Q1 MOSFET N Rout1 LR1_VOUT LR3_SEN C3 470u C4 0.1u
VCC3_3V Q3 MOSFET N Rout3 LR3_VOUT
LR1_DRV LR1_SEN
LR3_DRV
Rgnd1
Rgnd3
C7 470u
C8 0.1u
VCC3_3V Q2 MOSFET N Rout2 LR2_VOUT LR4_SEN C5 470u C6 0.1u
VCC3_3V Q4 MOSFET N Rout4 LR4_VOUT
LR2_DRV LR2_SEN
LR4_DRV
Rgnd2
Rgnd4
C9 470u
C10 0.1u
Figure10. F72830SG Application Circuit
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F72830
U3 DUAL 16 15 14 13 12 11 10 09
0.74V<= REF <= 1.04V 0.02V per step
SUS 1P05_DRV 1P05_SEN 1P5_SEN 1P5_DRV RAM_REF
1 2 3 4 5 6 7 8
LR1_SEN VDDA LR1_DRV SS LR2_DRV SCL LR2_SEN SDA LR3_SEN EN4 LR3_DRV EN3 LR4_DRV EN2 LR4_SEN GND F72830
C33 0.1u
C32 0.1u SCL SDA EN2 EN3 1P05_DRV
VRAM J38 Q28 1P05V 1 2 VSB 12V
RAM R55 1K R56 1K
ENx > 1.5V =>High
1P05_SEN R75 150
R73 200 D6 C50 470u C51 0.1u DUAL VRAM C37 1000u J40 C36 1000u D7
C34 X_0.1u
C35 X_0.1u
VCORE R62
VCORE L5 1P5_DRV 1u C38 0.1u 1P5_SEN R83 C39 470u Q26 L6 R66 R67 20K 22 Q27 C42 1000u C43 1000u C44 1000u VSB J36 1 EN3 2 EN2 1 3 J37 4.7u C40 1000u 150
Q31 R80 200 C56 470u
1P8V 1 2
10
VCC VSB 12V VCC 1 2 3 VDUAL CON3 J33 4 3 2 1 J42
C57 0.1u
D8 U4 J34 CON2 0.1u C41 1 6 RAM_REF 1 2 3 BOOT FB VREF GND 5
VCC
UGATE PHASE OCSET LGATE
2 8 7 4
R65
22
VRAM
default REF = 0.8V VOUT=[(Rout / Rgnd) + 1] * 0.8
VCORE
POWER CON
L7 2 4 VCC FB
0.78V< REF <= 1.2V
J35 2 1 9
F72815/F72814 TP1 R69 R70 R71 X_R DUAL R72 DUAL L8 0_R X_33 C45
DUAL POWER
R68 0.1/10W
X_47n
10 1u C46 0.1u U5 J39 CON2 0.1u C49 1 6 SUS 1 2 3 BOOT FB VREF GND 5
D9
C47 470u Q29
C48 1000u
VCC
UGATE PHASE OCSET LGATE
2 8 7 4
R74
22 L9 4.7u
VSUS
R76 R77
20K 22 Q30 C52 1000u C53 1000u C54 1000u
0.78V< REF <= 1.2V
J41 2 1
F72815/F72814 9 TP2 C55 X_47n
R79 R81 R82 X_R X_33
0_R
R78 0.1/10W
Note: Take note of what's kind of GND you using.
Figure11. F72830 and F72815 Practice Application Circuit
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